1. Field of the Invention
The present invention relates to an output buffer control circuit, and in particular, to an output buffer control circuit that performs high speed operation by generating a predetermined width of a pulse based on an output control signal.
2. Background of the Related Art
As shown in FIG. 1, a related art output buffer control circuit includes a data bus driving unit 102, a data bus equalizer 103, a data transmitter 104, a data output unit 105 and an output terminal pre-reset unit 106. The sense amplifier 101 detects data (DL1, DL2) of a cell (not shown). The data bus driving unit 102 drives data buses (DB1, DB2) based on first and second output signals received from the sense amplifier 101 when a sense amplifier enable signal (SP) becomes low level. The data bus equalizer 103 equalizes the data buses (DB1, DB2). The data transmitter 104 transmits data loaded on the data buses (DB1, DB2) when output enable signals (DU, DO) become low level and high level, respectively. The data output unit 105 generates an output signal via an output terminal (DOUT) based on the data transmitted from the data transmitter 104. The output terminal pre-reset unit 106 pre-resets the output terminal (DOUT) by delaying for a predetermined time and then logically processing the data transmitted from the data transmitter 104.
The data bus driving unit 102 includes NOR gates (NR1, NR2) for NORing the sense amplifier enable signal with the first and second output signals from the sense amplifier 101, respectively. The data bus driving unit 102 also includes NMOS transistors (NM1, NM2) that turn on or off based on the respective output signals from the NOR gates (NR1, NR2). The NMOS transistors (NM1, NM2), respectively, drive the data buses (DB1, DB2).
The data bus equalizer 103 includes NMOS transistors (NM3-NM5), whose gates receive an output enable signal (DU). The NMOS transistors (NM3, NM4) are connected to the data buses (DB1, DB2), respectively, and their drains receive a voltage (Vcc). The NMOS transistor (NM5) is connected between the data buses (DB1, DB2).
In the data transmitter 104, the output enable signal (DU) is applied to the inverting control terminal of transmission gates (TG1, TG2). The transmission gates (TG1, TG2) are coupled to the data buses (DB1, DB2), respectively. Sources of PMOS transistors (PM1, PM2) receive the voltage (Vcc). Gates of the PMOS transistors (PM1, PM2) and control terminals of the transmission gates (TG1, TG2) receive an output enable signal (DO). Drains of the PMOS transistors (PM1, PM2) are respectively coupled to output terminals of the transmission gates (TG1, TG2) at the data buses (DB1, DB2).
In the data output unit 105, a first output signal from the data transmitter 104 is applied through series inverters (IN1, IN2) to a PMOS transistor (PM3) gate while its source receives the voltage (Vcc). A second output signal from the data transmitter 104 is applied through an inverter (IN3) to an NMOS transistor (NM6) gate while its source is grounded. Drains of the PMOS transistor (PM3) and the NMOS transistor (NM6) are commonly connected to the output terminal (DOUT).
The output terminal pre-reset unit 106 includes a plurality of series inverters (IN4-IN6) and (IN7-IN9) for sequentially delaying respective terminal signals (DP1, DP2) from the data output unit 105. The output terminal pre-reset unit 106 further includes a NAND gate (NA1) for NANDing the terminal signal (DP1) and an output signal from the inverter (IN6), an inverter (IN10) for inverting an output signal from the NAND gate (NA1), a NOR gate (NR3) for NORing the terminal signal (DP2) and an output signal from the inverter (IN9), an NMOS transistor (NM7) for applying a voltage (Vcc) to the output terminal (DOUTf when an output signal from the NOR gate (NR3) is high level and an NMOS transistor (NM8) for grounding the output terminal (DOUT) when an output signal from the inverter (IN10) is high level.
Operations of the related art output buffer control circuit will now be described.
In the operation of a memory device, when a low level of data (DL1) is input to the sense amplifier 101, the NMOS transistor (NM1) is turned on because the NOR gate (NR1) NORs a low level of the sense amplifier enable signal (SP) and a low level of the first output signal from the sense amplifier 101. The data (DL1, DL2) and the sense amplifier enable signal (SP) are shown in FIGS. 2A-2B. Further, the NMOS transistor (NM2) is turned off because the NOR gate (NR2) NORs the low sense amplifier enable signal (SP) and a high level of the second output signal from the sense amplifier 101.
Then, in the data bus equalizer 103, the data bus (DB1) becomes low level with the NMOS transistor (NM1) turned on, and the data bus (DB2) becomes high level with the NMOS transistor (NM2) turned off.
Accordingly, in the data transmitter 104 because the output enable signals (DU, DO) become low and high level, respectively, output signals from the data bus equalizer 103 are outputted to the data output unit 105 through the transmission gates TG1, TG2).
Next, in the data output unit 105, the terminal signal (DP1) becomes low level through the inverters (IN1, IN2) in accordance with the low level of the first output signal output by the data transmitter 104. Further, the terminal signal (DP2) becomes low level through the inverter (IN3) in accordance with the high level of the second output signal output by from the data transmitter 104.
Therefore, only the PMOS transistor (PM3) is turned on in the data output unit 105 and the output terminal (DOUT) becomes high level.
When the data (DL1) is changed from low level to high level, while the sense amplifier enable signal (SP) is high level, in the data bus driving unit 102 the output signals from the NOR gates (NR1, NR2) become low level to keep the NMOS transistors (NM1, NM2) turned off. Then, the output enable signals (DU, DO) shown in FIG. 2C, become high and low level, respectively, to disable the transmission gates (TG1, TG2) in the data transmitter 104.
In the data bus equalizer 103, the NMOS transistors (NM3 (NM5) are turned on in accordance with the high level of the output enable signal (DU) to equalize the high level data buses (DB1, DB2). In the data transmitter 104, the PMOS transistors (PM1, PM2) are turned on in accordance with the low level of the output enable signal (DO) to output the voltage (Vcc) to the data output unit (105).
Next, in the data output unit 105, the terminal signals (DP1, DP2) become high and low level, respectively, through the inverters (IN1-IN3) in accordance with the voltage (Vcc) output by the data transmitter 104. As a result, the PMOS transistor (PM3) and the NMOS transistor (NM6) are kept turned off to keep the output terminal (DOUT) at the previous high level.
Then, during the delay time of the inverters (IN4-IN9) in the output terminal pre-reset unit 106, the NAND gate (NA1) NANDs the high level of the terminal signal (DP1) and a high level of an output signal from the inverter (IN6). The inverter (IN10) inverts the NANDed signal to high level to turn on the NMOS transistor (NM8). During the delay time, the NOR gate (NR3) NORs the low level of the terminal signal (DP2) and a high level of an output signal from the inverter (IN9) to keep the NMOS transistor (NM7) off.
Therefore, with the NMOS transistor (NM8) turned on, the level of the output terminal (DOUT) is lowered to a three-phase (state) level.
After the delay time of the inverters (IN4-IN9) elapses, the output signal from the NAND gate (NA1) becomes high level. Subsequently, the DR1 signal becomes low level through the inverter (IN1). As a result, the NMOS transistor (NM8) is turned off. After the delay time, the output signal from the NOR gate (NR3) is maintained as low level, and consequently, the NMOS transistor (NM7) is kept off.
Next, when the sense amplifier enable signal (SP) becomes low level and the output enable signals (DU, DO) become low and high level, respectively, the output signals from the NOR gates (NR1, NR2) become low and high level, respectively. In this manner, the NMOS transistor (NM1) is kept off and the NMOS transistor (NM2) is turned on.
Thus, the data bus (DB1) is kept high level and the data bus (DB2) becomes low level in the data bus equalizer 103, and the high and low levels of the respective data buses (DB1, DB2) are output to the data output unit 105 through the transmission gates (TG1, TG2).
Accordingly, in the data output unit 105, the terminal signal (DP1) becomes high level through the inverters (IN1, IN2), and the terminal signal (DP2) becomes high level through the inverter (IN3). In the data output unit 105, only the NMOS transistor (NM6) is turned on to obtain a low level at the output terminal (DOUT).
Then, the data (DL1) detected from the sense amplifier 101 is changed from high level to low level. In this manner, during the delay time of the inverters (IN4-IN9) in the pre-reset unit 106, an output signal from the NAND gate (NA1) becomes high level. As a result, an output signal from the inverter (IN10) becomes low level to turn off the NMOS transistor (NM8). An output signal from the NOR gate (NR3) becomes high level to turn on the NMOS transistor (NM7), As a result, the output terminal (DOUT) is raised to a three-phase (state) level.
Then, when the sense amplifier enable signal (SP) becomes low level and the output enable signals (DU, DO) become low and high level, respectively, the data DL1, DL2) detected from the sense amplifier 101 are input to the data bus driving unit 102. The data (DL1, DL2) sequentially pass through the data bus equalizer 103 and the data transmitter 104, and are input to the data output unit 105, Consequently, the PMOS transistor (PM3) alone is turned on, and the output terminal (DOUT) becomes high level.
The above-described operation is carried out as shown in the timing diagrams in FIGS. 2A-2F.
However, the related art output buffer control circuit has various disadvantages in that an erroneous operation is caused or the operation speed is slowed down because the output voltage cannot assume a three-phase (state) level when a pulse width narrows according to an address transition detection.
In particular, because the pulse width, according to the address transition detection, cannot be made wider in a high speed memory device other methods are required. Thus, a need exists for a high speed output buffer control circuit.